In balanced RFIC (Radio Frequency Integrated Circuit) mixer design, it is often desirable to split an incoming Radio Frequency (RF) signal into two differential signals. Optimally, these differential signals should be 180.degree. out of phase and equal in amplitude.
The prior art has proposed several phase splitting circuits for accomplishing these goals. The ideal phase splitter will generate two differential signals from one RF signal. These signals will be as close to 180.degree. out of phase as possible while having as close to equal amplitude as possible. The output signals do not need to be the same amplitude as the input signal. If generated differential signals are more or less than 180.degree. out of phase, the signals are said to be unbalanced by that difference. Similarly, the generated differential signals are also said to be unbalanced by the amount their amplitudes differ in decibels.
The phase splitter has been implemented using either passive or active components. However, passive components, such as capacitors and inductors, tend to be lossy in RFICs. Additionally, they are ill suited for broad band applications. Moreover, since they occupy a large die area, they are more expensive than their active counterparts. Accordingly, it is often a goal in RFIC design to use active components whatsoever possible.
It Is especially important to have balanced phase and amplitude of the differential signals in applications such as a double balanced up-mixer. Perfectly balanced signals to the mixer minimize the local signal (LO) leakage level at the RF input port and greatly simplify the design of LO filtering. It is therefore an additional goal of RFIC design to create a robust phase splitter circuit providing both accurate phase and amplitude balance.
FIG. 1A shows a prior art single FET phase splitter 100. The phase splitter 100 of FIG. 1A comprises a single FET 102, an input voltage V.sub.INPUT 104, and two output voltages, V.sub.out1 106, and V.sub.out2 108. V.sub.out1 106 should optimally be 180.degree. out of phase with V.sub.out2 108. This may be accomplished if this circuit is used at low frequencies. However, this phase splitter is unable to operate at higher frequencies, which is required in most RF applications. Adding sophisticated imbalance circuitry solves this deficiency to some extent. This circuitry is detailed in M. Goldfarb et al., A Novel MMIC Biphase Modulator with Variable Gain Using Enhancement-Mode FETs suitable for 3v Wireless Applications, p. 99, PROC. 1994, IEEE, MICROWAVE AND MILLIMETER-WAVE MONOLITHIC CIRS. SYMP. However, there may still be a 1 dB amplitude unbalance and an 8.degree. phase unbalance when the circuit is operating between 700 MHz and 1.7 GHz. Moreover, the ability to operate at high frequency is achieved only with greater circuit complexity, increased die area, and increased current consumption. This circuit, therefore, is unacceptable for use in higher frequency RFIC design.
In FIG. 1B, another active phase splitter 120 is shown. This circuit was used in the article by L. Devlin et al., A 2.4 GHz Single Chip Transceiver, p. 23, PROC. 1993 IEEE MICROWAVE AND MILLIMETER-WAVE MONOLITHIC CIRS. SYMP. Two transistors 126 and 128 are provided which are connected in a common gate and common source configuration, respectively. The input signal is coupled to the source of transistor 126 through an AC coupling capacitor 122. At the same time, the input signal is fed to the gate of transistor 128. An AC bypass capacitor 124 is provided to bypass the biasing resistor 129. However, in this configuration, the AC coupling capacitance and the bypass capacitance 122, 124 need to be adjusted separately at each specific operating frequency. Accordingly, although this circuit may achieve less than 0.5 dB amplitude unbalance and .+-.5.degree. phase unbalance, it is applicable only in narrow band applications, due to the necessity of separately tuning each capacitor.
FIG. 1C shows a differential amplifier configured as a phase splitter. The impedance at node S.sub.1 149 is critical in balancing the outputs V.sub.out1 144 and V.sub.out2 146. Each transistor should ideally receive an equal portion of the input signal. To accomplish this, the impedance at node S.sub.1 149 should be as large as possible or be implemented using as large an R.sub.s as possible. This may be accomplished if R.sub.s 132 is replaced with a constant current source that has infinite impedance. Thus, using a common current source in place of R.sub.s 132, transistors 140, 142 will receive the same amount of input signal and both outputs 144, 146 will be balanced.
The two transistors 140,142 will receive the same amount of input signal due to the infinite impedance of the current source. Because of this, the AC input signal drops across the input impedance of transistors 140, 142 equally. Assuming the same DC bias point, transistors 140, 142 should have the same input impedance. Accordingly, assuming R.sub.s to be infinite, .nu..sub.gs1 =-.nu..sub.gs2. This effectively reduces the circuit 130 to a simple voltage divider circuit, and therefore the following relationship holds true: ##EQU1## Thus, each transistor 140, 142 will receive half the input signal 138. Accordingly, the output signals 144, 146 will be 180.degree. out of phase and equal in amplitude.
Unfortunately, in RFIC design it is not possible to replace R.sub.s with an ideal current source. A non-ideal current source such as active devices have strong parasitic characteristics at high frequencies. Further, typical wireless devices often have low V.sub.dd requirements. For example, in a typical portable wireless communications application, V.sub.dd may be less than 3 volts or even 2 volts. Accordingly, it may not be feasible in most portable wireless applications to have an on-chip current source in place of R.sub.s, since the biasing voltage V.sub.ds across the drain and source of the current source transistor should be 1 volt to 1.5 volts. This circuit may, however, be used in portable wireless applications with a low V.sub.dd requirement if the value of R.sub.s is limited.
As previously mentioned, an infinite R.sub.s is desirable because, as R.sub.s approaches infinity, the above mentioned relationship of .nu..sub.gs1 =-.nu..sub.gs2 exists, and the output signals will be completely balanced. At the other extreme, as R.sub.s approaches 0, the source of transistor 140 will effectively short circuit to ground, and the input voltage drop across transistor 142 will also approach 0. Therefore, at small values of R.sub.s, .nu..sub.gs2 will approach 0, and v.sub.gs1 will approach V.sub.INPUT. In general cases, .vertline..nu..sub.gs1 .vertline.&gt;.vertline..nu..sub.gs2 .vertline..Therefore, a balanced differential signal using the circuit 130 is typically not feasible.
The circuit 150 of FIG. 1D shows the circuit of FIG. 1C with typical values for the individual components inserted. This circuit was used to produce the plot shown in FIG. 1E. The plot 180 shown in FIG. 1E represents the simulated amplitude and phase differences between the output signals V.sub.01 170 and V.sub.02 172. As shown by the curve 182, the amplitude of output V.sub.01 is larger than that of output V.sub.02 by 6.about.8 dB. Moreover, as further shown by curve 184, the phase differences range between 180.degree. to 163.degree. at higher frequencies. This wide range of unbalance in the phase and amplitude is a result of the difficulties mentioned above in choosing a value for R.sub.s.
One solution to this problem proposed in U.S. Pat. No. 5,068,621 is to compensate for or bypass some of the input signal V.sub.INPUT. A circuit 190 implementing this solution is depicted in FIG. 1F where part of the input signal is fed via impedance Z2 to the source of each transistor 192, 194. Preferably, Z2 is selected in relation to the source impedance Z1=R.sub.s so as to cancel any current that would otherwise flow through R.sub.s. However, the circuits implementing this solution are not capable of adjusting amplitude and phase differences separately. Moreover, these circuits are even more complicated to design and implement than the differential circuit.
Accordingly, it is an object of the present invention to overcome the disadvantages of the prior art.